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July 29, 2013 | Optimising design of multitasking applications on multiprocessor architectures

With the emergence of multiprocessor systems and distributed architectures on the consumer market (multimedia and automotive), optimising embedded architectures has become a major challenge to ensure operating performance.

CEA LIST tackles this from several angles. If the systems can be built on architectures integrating specific hardware elements (computing accelerators), the aim is to research which combinations of computing architecture / processing algorithms optimise computing time, performance and cost (particularly energy costs). For this purpose, CEA LIST has developed a parallel architecture evaluation and programming environment as part of the Carnot COTS project, which enables users to optimise their choice of programming style and target architecture for a given application.

In a less “free” context (constraints on the hardware architecture, compliance with a specific standard) or if the functions to be performed are not amenable to parallel data processing (video, signal), the problem has to be addressed in a more general way, as a set of functions to be performed over time on distributed computing resources. CEA LIST has thus developed an original approach, combining exact and heuristic formal methods by approximation – to meet this general requirement – with the analysis software Qompass.

Optimising resources involves three levels of architecture: applications (what users want and see), processors (hardware computing resources) and tasks (normal concept aimed at creating virtual subdivisions of processes on the same resource).

The design of the final system is then based on two allocation levels and one validation action:

  • placement associates functions with tasks (level of parallelism required),
  • partitioning allocates available computing resources to tasks,
  • scheduling calculates an implementation plan (typically allocation of priorities to tasks) to guarantee the quality of service expected (typically adherence to deadlines).

To deal with these problems in a general way, CEA LIST, in collaboration with two researchers and international experts (Prof. Marco di Natale[1] and Haibo Zeng[2]), has developed a mixed approach combining formal and heuristic calculations. By scaling up to hundreds of functions deployed on about ten processors, this general solution can be regarded as innovative compared with exact solutions, which are quickly swamped by the effect of combinatorics as soon as distribution is over several processors.

This research, initiated as part of the European INTERESTED project[3] (2008-2011), particularly addresses the competitive challenges facing the automotive industry by optimising embedded resources, thereby guaranteeing application performance and real-time behaviour.

Parallel studies are also underway to apply and integrate these results with the AUTOSAR standard. They could then be incorporated into an optimisation module associated with the AUTOSAR design tools developed by various software publishers in the field, such as Esterel Technologies.

[1]Pr. Marco di Natale – Scuola Superiore Santa Anna & Berkeley University

[2]Haibo Zeng - Mac Gill University

[3]The FP7 INTERESTED project – INTERoperable Embedded Systems Toolchain for Enhanced rapid Design – brought together a consortium of leading-edge European embedded system tool vendors (AbsInt Angewandte Informatik (Germany), Atego (UK), CEA (France), Esterel Technologies (France), UNIS (Czech Republic), Evidence (Italy), Symtavision (Germany), Sysgo (Germany) and TTTech Computertechnik (Austria)), as well as major European tool users (Airbus (France), Magneti Marelli Powertrain (Italy), Siemens Mobility Division, Rail Automation (Germany) and Thales (France)).