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Computing architectures

List institute capitalises on most recent computing technologies in order to develop sophisticated and energetically efficient architectures, adapted to embedded applications that request an important computing power, an optimised silicon surface and guaranteed quality of service such as videosurveillance, transport or smart manufacturing.

We optimise the adequacy of algorithms vs architecture. We design original architectures – especially for dynamic applications – and we define their hardware integration on GPU, FPGA and multi-core standard market processors or on specific ones. Within the frame of collaboration agreements we work with industrial companies in order to define new processors generations or the tools that will help designing them.
Privileged access to most recent technologies from the main European technology providers gives us the opportunity to design integrated components at the best international state-of-the-art level.

Among our academic partners

IRISA (Rennes, France), LEAB (Bourgogne, France), LAB-LTIC (Bretagne, France), LEAT (Nice, France), CSEM (Switzerland), OFFIS (Germany)


  • Complete management of the domain’s 3 key-elements : applications, electronics and system software
  • Expertise on linked applications : vision and image processing

Major technologies

Vision systems’ architectures


CEA LETI and List institutes have created a smart retina in 3D stacking technology including space, consumption and speed constraints. The objective here is to be able to capture a visual scene at more than 1000 images/second speed thanks to an instant processing architecture in order to identify the scene’s points of interest in real time. This new kind of architectures allows an increased connectivity between analog and digital parts and on the other hand, allows a decreased energy consumption: processing latency divided per 15, power of calculation multiplied per 100 and energy efficiency 10 times superior.


Parts inspection at very high-speed industrial chains, drones, domotics, security, person assistance, entertainment, smart home, augmented reality

  • ANR project RETINE


Embedded systems parallel architectures’ design environment


In order to evaluate precisely and rapidly the different multicore components’ architectural options, List institute developed an environment for parallel architectures’ exploration based on precise instruction games simulators and on a controlled TLM control and communication infrastructure. The whole combination remains compatible with traditional hardware design flows. It is also the opportunity to maintain the same development environment from exploration phases to architectures’ validation by emulation.
The platform is reinforced by complementary information concerning temperature, energy consumption and failure models. This complementary information helps identifying the most sensitive-to-failure architecture blocks and thus focusing optimisation efforts where most needed for reliability requests. Thermal processing can be predicted at the very first design step with a modelling error below 5%.


Multi-core circuits optimised design


Neuromorphic architectures



Inspired by the human brain neurons’ function, List institute sets-up very low energy consumption electronic components and their associated algorithms for cognitive calculation. This way we settled an architectural exploration methodology in order to define in the most possible efficient way neurones’ structure that can answer a specific application. List developed also circuit architectures adapted to different memory technologies (PCM, RRAM…) in order to set-up functions for neuro-inspired data processing. We created a dedicated platform to study these architectures including learning and training methods but also functional or semi-physical models. We can this way study their robustness according to variability and nano/CMOS co-integration.


Identification and dimensional or sensorial control for industrial use, information cognitive processing, memory calculation, natural signals processing

  • European project FIPS